1. Field
The following description relates to a semiconductor device.
2. Description of Related Art
In a double diffused metal-oxide-semiconductor (DMOS) transistor, a channel of a metal-oxide-semiconductor (MOS) transistor mainly used as a semiconductor device for high voltage is usually formed horizontally to a substrate surface. However, recently, according to a reduction of design approach for semiconductor devices, a trench MOS transistor, such as a MOS transistor for high voltage that has a vertical channel that is easily high integrated, has come into the spotlight. Briefly considering the structure of a trench MOS transistor, in a trench MOS transistor a drain is arranged at a back side of a substrate; a source is arranged on a front side of a substrate; a gate is arranged inside a trench which is indented into the substrate surface; and a current flows up and down along a side wall of the trench, in the substrate.
FIG. 1 illustrates a plan view of an active region and an edge region according to a conventional semiconductor device, and FIG. 2 illustrates a sectional view taken on line A-B of FIG. 1.
Referring to FIGS. 1 and 2, a semiconductor is divided into an active region (X) and an edge region (Y). The active region (X) includes a trench 100 and a trench transistor cell 101-1 having contacts 101 inside an active region. The edge region (Y) includes a contact pattern configured to transfer a voltage to an electrode. As shown in FIG. 2, a first insulating film 210 is formed on a substrate 200. A shield structure 220 is formed on the first insulating film 210. A second insulating film 230, a gate structure 240, and a third insulating film 250 are all formed on the upper surface of the substrate. Contact holes 231, 251 are formed in the second insulating film 230 and in the third insulating film 250 respectively.
With respect to the edge region (Y), laminations of the shield structure 220 and the gate structure 240 are unavoidable, because it is necessary to manufacture these structures in successive, stacked layers. However, the wider the stacked extent is, the more easily the gate-to-source current (IGSS) characteristic, such as leakage current of gate/source or gate/drain for the transistor is decreased. Therefore, aspects of semiconductor performance are affected.
Also, due to the above-described stacked structure, absolute generation of high differences in the structure of the semiconductor device is unavoidable. For this reason, there are defects of a defocus in the photo process and defects of a passivation in the etch process.